Fabricating Memory Devices with Optimized Gate Oxide Thickness

ABSTRACT

The present disclosure describes apparatuses and methods for manufacturing programmable memory devices with optimized gate oxide thickness. In some aspects, lithography masks are used to fabricate oxide gates for programmable memory devices of an integrated-circuit (IC) die that are thinner than oxide gates fabricated for processor core devices of the IC die. In other aspects, lithography masks are used to fabricate oxide gates for the programmable memory devices of the IC die such that they are thicker than the oxide gates fabricated for the processor core devices of the IC die. By so doing, the programmable memory devices can be manufactured with optimized gate oxide thickness that may reduce programming voltage or increase device reliability of the programmable memory devices.

CROSS REFERENCE TO RELATED APPLICATION

This application is a divisional of and claims priority to U.S. patentapplication Ser. No. 15/799,776, filed Oct. 31, 2017, which in turnclaims priority to U.S. Provisional Patent Application Ser. No.62/415,145, filed Oct. 31, 2016, the disclosures of which areincorporated by reference herein in their entirety.

BACKGROUND

Conventional techniques for fabricating an integrated-circuit (IC) dierely on a single lithography cycle to pattern oxide gates of devicetransistors of the IC die. This results in device transistors of the ICdie having oxide gates with a similar thickness, which governs devicefunctionality and performance over a particular voltage range. In somecases, however, the device transistors of the IC die are configured tosupport multiple types of devices that operate at different respectivevoltage levels, such as memory devices, processor core devices,input/output (I/O) devices, and the like. To ensure correct operation ofthe multiple types of device transistors at different respective voltagelevels, IC dies often include additional circuitry for voltageregulation or isolation to prevent lower-voltage transistor devices frombeing damaged by high voltage signals of other device types. Theaddition of this regulation and protection circuitry, however, can beexpensive in terms of power, circuit complexity, or design space of anIC die.

SUMMARY

This summary is provided to introduce subject matter that is furtherdescribed in the Detailed Description and Drawings. Accordingly, thisSummary should not be considered to describe essential features nor usedto limit the scope of the claimed subject matter.

In some aspects, a method is described that exposes respective gateareas of programmable memory devices and processor core devices of an ICdie and occludes gate areas of I/O devices of the IC die. After etchinga first layer of oxide material from the exposed respective gate areasof the programmable memory devices and the processor core devices, asecond layer of oxide material is formed on the IC die. Gate areas ofthe programmable memory devices are then exposed and respective gateareas of the processor core devices and the I/O devices are occluded.The method then etches the second layer of oxide material from theexposed gate areas of the programmable memory devices, after which athird layer of oxide material is formed on the IC die. This can beeffective to fabricate, on the IC die, a thinner oxide gate for theprogrammable memory devices than that of the processor core devices.

In other aspects, a method is described that exposes respective gateareas of programmable memory devices and processor core devices of an ICdie and occludes gate areas of I/O devices of the IC die. After etchinga first layer of oxide material from the exposed respective gate areasof the programmable memory devices and the processor core devices, asecond layer of oxide material is formed on the IC die. Gate areas ofthe processor core devices are then exposed and the respective gateareas of the programmable memory devices and the I/O devices areoccluded. The method then etches the second layer of oxide material fromthe exposed gate areas of the processor core devices, after which athird layer of oxide material is formed on the IC die. This can beeffective to fabricate, on the IC die, a thicker oxide gate for theprogrammable memory devices than that of the processor core devices.

In other aspects, an IC die is described that comprises I/O deviceshaving oxide gates of a first thickness, processor core devices havingoxide gates of a second thickness, and non-volatile programmable memorydevices having oxide gates of a third thickness. The third thickness ofthe oxide gates of the non-volatile memory devices may be different fromthe first thickness of the oxide gates of the I/O devices and the secondthickness of the oxide gates of the processor core devices. The IC diealso includes a memory device programming circuit that is configured toprogram the non-volatile memory devices by altering respective oxidegates of the non-volatile memory devices using a programming voltagethat is approximately twice a voltage at which the processor coredevices operate.

The details of one or more implementations are set forth in theaccompanying drawings and the following description. Other features andadvantages will be apparent from the description and drawings, and fromthe claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The details of one or more aspects of fabricating memory devices withoptimized gate oxide thickness are described below. The use of the samereference numbers in different instances in the description and thefigures may indicate like elements:

FIG. 1 illustrates an example operating environment that includessemiconductor manufacturing tools for fabricating an IC die.

FIG. 2 illustrates example cross sections of IC dies in accordance withone or more aspects.

FIG. 3 illustrates an example method for fabricating oxide gates ofprogrammable memory devices that are thinner than other oxide gates ofan IC die.

FIG. 4 illustrates example cross sections of an IC die fabricated toprovide programmable memory device oxide gates that are thinner thanother oxide gates of the IC die.

FIG. 5 illustrates an example method for fabricating oxide gates ofprogrammable memory devices that are thicker that other oxide gates ofan IC die.

FIG. 6 illustrates example cross sections of an IC die fabricated toprovide programmable memory device oxide gates that are thicker thanother oxide gates of the IC die.

FIG. 7 illustrates an example SoC component that includes multiple typesof IC devices.

DETAILED DESCRIPTION

Conventional techniques of integrated-circuit (IC) die fabricationtypically rely on a single lithography cycle to pattern oxide gates oftransistors that are configured as multiple types of devices. Thisresults in oxide gates of the multiple types of devices being a samethickness, which leads to design issues and other challenges becauseeach type of device often has different respective operational orperformance requirements. For example, transistors of an IC die may beimplemented as memory devices, processor core devices, and input/output(I/O) devices, all of which have different operational parameters. Thesedifferent operational parameters may include operating voltages at whichsome transistors (e.g., processor core devices) of the IC switch orprogramming voltages for physically altering gate structure of othertransistors (e.g., memory devices) of the IC.

In particular, the process for programming a programmable memory deviceoften requires applying a programming voltage to physically break downthe oxide gate of the programmable memory device (e.g., an electronicanti-fuse) in order to create a conductive path that is effective to“set” a bit of the device. When the programmable memory device has angate oxide thickness that is the same as processor core devices of theIC die, the programming voltage used to break down the oxide gate of theprogrammable memory device can be a factor of three to four times higherthan that of the voltage at which the processor core device functions.Accommodating such a high programming voltage within the IC dietypically involves special design considerations to mitigate voltagestress on other structures of the IC die. Additionally, generating aprogramming voltage that is three to four times higher than otheroperating voltages of the IC die may require charge pump circuitry,designated external power voltage supplies, additional printed circuitboard traces, or dedicated SoC component pins to bring the higherprogramming voltage into the IC die.

This disclosure describes apparatuses and techniques for fabricatingmemory devices with optimized gate oxide thickness. In some aspects, oneor more lithography masks are used to fabricate oxide gates forprogrammable memory devices of an integrated-circuit (IC) die that arethinner than oxide gates fabricated for processor core devices of the ICdie. In other aspects, one or more lithography masks are used tofabricate the oxide gates for the programmable memory devices of the ICdie such that they are thicker than the oxide gates fabricated for theprocessor core devices of the IC die. By so doing, the programmablememory devices can be manufactured with optimized gate oxide thicknessthat may reduce programming voltage or increase device reliability ofthe programmable memory devices.

These and other aspects described herein may be implemented tofabricate, with multiple lithography cycles, an IC die with multipledevices types with oxide gates of different respective thicknesses. Insome cases, oxide gates of programmable memory devices, such as one-timeprogrammable (OTP) memory or multiple-time programmable (MTP) memory,are formed with a thickness optimized for lower programming voltage orreduced gate leakage. Alternately or additionally, one of the multiplelithography cycles may be used to optimize other surface topography ofthe programmable memory device, such as the oxide gate interface, inorder to enhance programming characteristics.

The following discussion describes an operating environment, techniquesthat may be employed in the operating environment, and a System-on-Chip(SoC) in which components of the operating environment can be embodied.In the context of the present disclosure, reference is made to theoperating environment by way of example only.

Operating Environment

FIG. 1 illustrates an example operating environment 100 that includes alithography tool 102, an etch tool 104, and a deposition tool 106 inaccordance with one or more aspects. Generally, these tools process asemiconductor wafer 108 to fabricate devices and circuitry ofintegrated-circuits (ICs) on the semiconductor wafer 108. Afterpatterning and fabrication, the semiconductor wafer 108 can be cut orsingulated into individual IC dies for incorporation into any suitabletype of component, such as a System-on-Chip (SoC) component, anApplication-Specific Integrated-Circuit (ASIC) component, aSystem-in-Package (SIP) component, a memory component, a microprocessorcomponent, and the like.

Generally, the lithography tool 102 includes mechanisms and controls forpatterning a layer of photoresist material on the semiconductor wafer108. In some cases, the lithography tool 102 is configurable to alter ormodify a layer of the photoresist material on the semiconductor wafer108 in a predefined pattern. In this example, the lithography tool 102includes a control system 110, light source 112, wafer mechanism 114,and mask mechanism 116 for implementing lithography operations. Thecontrol system 110 is configured to establish and maintain parametersfor patterning the layer of photoresist material, such as lightradiation intensity, light radiation exposure time, and alignment of thesemiconductor wafer 108 relative to masks 118, 120 via the wafermechanism 114 or the mask mechanism 116. A hardware-based processor (notshown) of the lithography tool 102 may execute processor-executableinstructions from a memory device to implement the control system 110 ora user interface associated therewith. To pattern the layer ofphotoresist material, the light source 112 (or an energy source)radiates, through the mask, any suitable type of light or radiation,such as ultraviolet (UV) light, extreme ultraviolet (EUV) light, x-rayradiation, ion beams, and the like.

In the context of the operating environment 100, the lithography tool102 is configured as part of a semiconductor wafer processing line inwhich the lithography tool 102 receives and processes the semiconductorwafer 108 as a work in process (WIP) semiconductor wafer towards a finalproduct. The semiconductor wafer 108 includes multiple layers ofsemiconductor materials that can be processed to fabricate a pluralityof like IC die on the semiconductor wafer 108. Typically, thelithography tool 102 receives the semiconductor wafer 108 coated with alayer of photoresist material. In such cases, the layer of photoresistmaterial may cover a most-recently deposited layer of semiconductormaterial from which features of the IC die are to be fabricated.

The deposited layer of semiconductor material may include any suitabletype of material, such as a dielectric or conductive material having anelectrical or physical property configured to provide necessaryelectrical or physical performance attributes of features to beingfabricated on the IC die. In order to pattern the layer of photoresistmaterial over the layer of semiconductor material, light (or energy) isradiated from the light source 112 through a mask that is configured topermit irradiation of some portions of the layer of photoresist materialwhile preventing irradiation of other portions of the layer ofphotoresist material. As illustrated in FIG. 1, multiple masks 118, 120are available, each mask for a particular lithography cycle or featuresset. By way of example, a first mask 118 can create a particular patternto fabricate a first set of features on the semiconductor wafer 108during a first lithography cycle and a second mask 120 can createanother pattern to fabricate a second set of features on thesemiconductor wafer 108 during a second lithography cycle.

After the light source 112 radiates light through the one of the masks118, 120 to pattern a layer of the photoresist material covering thelayer of semiconductor material, the semiconductor wafer 108 isdeveloped on a developing tool (not shown) to remove undesired photoresist and expose portions of the layer of semiconductor material forfurther processing. A positive photoresist material may be used, inwhich case portions of irradiated portions of photoresist materialbecome soluble when developed and are removed using a developersolution. Alternatively, a negative photoresist material may be used, inwhich case portions of photoresist material that are not irradiatedbecome soluble when developed and are removed using a developersolution.

In this example, the etch tool 104 of the operating environment 100 isconfigured to receive and process the semiconductor wafer 108 after thesemiconductor wafer has been developed. The etch tool 104 includesmechanisms and controls for removing, via an etch process, semiconductormaterials from the surface of the semiconductor wafer 108. The etch tool104 includes a control system 122, an etch chamber 124, a wafermechanism 126, and a fluid mechanism 126 to implement various etchingoperations. The control system 122 establishes and maintains parametersfor etching. In some cases, a hardware-based processor of the etch tool104 executes processor-executable instructions from a memory device toimplement the control system 122 or a user interface associatedtherewith. The etch chamber 124 is a chamber in which the semiconductorwafer 108 is positioned and exposed to an etchant fluid, such as achemical liquid, plasma gas, and the like. The wafer mechanism 126transports the semiconductor wafer 108 into and out of the etch chamber124. To facilitate etching, the fluid mechanism 128 of the etch tool 104disperses the etchant fluid into the chamber.

The semiconductor wafer 108, with portions of the layer of semiconductormaterial exposed according to the pattern dictated by either the mask118 or the mask 120, is presented to the etch tool 104 for etching.During the etching process, the exposed portions of the layer ofsemiconductor material on the semiconductor wafer 108 (e.g., portions ofthe layer of semiconductor material not remaining coated by photoresistmaterial after the semiconductor wafer 108 is developed) are removed.Unexposed portions of the layer of semiconductor material (e.g.,portions of the layer of semiconductor material remaining coated byphotoresist material after the semiconductor wafer 108 is developed) areprotected and not removed. After etching, the semiconductor wafer 108 ispresented to an ashing tool (not shown), where all remaining photoresistis removed from the semiconductor wafer 108.

The deposition tool 106 of the operating environment 100 is configuredto receive the semiconductor wafer 108 after removal of the photoresistvia the ashing tool. Generally, the deposition tool 106 includesmechanisms and controls for depositing a layer of semiconductor materialon a semiconductor wafer. In this example, the deposition tool 106includes a control system 130, a deposition chamber 132, a wafermechanism 134, a fluid mechanism 136, and a thermal mechanism 138. Thecontrol system 130 establishes and maintains parameters for thedeposition process, and may control the other components of thedeposition tool 106 to implement various deposition operations. In somecases, a hardware-based processor (not shown) of the deposition tool 106executes processor-executable instructions from a memory device toimplement the control system 130 or a user interface associatedtherewith.

The deposition chamber 132 is a chamber in which the semiconductor wafer108 is positioned via the wafer mechanism 134. In the deposition chamber132, the semiconductor wafer 108 is exposed to environmental conditions(e.g., temperature and pressure) and materials effective to deposit thelayer of the semiconductor material on the wafer. During the depositionprocess, the fluid mechanism typically introduces fluids into thechamber in a gaseous or chemical vapor form for deposit on thesemiconductor wafer 108. The thermal mechanism 138 establishes andcontrols thermal and other environmental conditions, such as pressure,in the deposition chamber 132 during the deposition process. Thedeposition process can be implemented to form, in whole or part, anysuitable type of semiconductor or device structure (e.g., transistors ordiodes). In some cases, a layer of material that is deposited on thesemiconductor wafer 108 has properties or is configured to providetransistor gate functionality for devices embodied on the semiconductorwafer. Such a layer of material can be, for example, a layer of asilicon oxynitride material, a layer of silicon dioxide material, or alayer of silicon nitride material.

In the context of the operating environment 100, the semiconductor wafer108 is presented to the deposition tool 106 in order to deposit a newlayer of semiconductor material. In some cases, the semiconductor wafer108 is presented with portions of the previous layer of semiconductormaterial remaining. Depending on features being fabricated on thesemiconductor wafer 108, the previous layer of semiconductor materialmay be a dielectric or conductive material having an electrical orphysical property configured to provide necessary electrical or physicalperformance attributes for the features to being fabricated on the ICdie. After the deposition of a new layer of semiconductor material usingthe deposition tool 106, another layer of photoresist material can beapplied to the semiconductor wafer 108 using a coating tool (not shown)for additional patterning via an additional lithography cycle. Thesetools of the operating environment may be implemented to perform anysuitable number of lithography, etching, or deposition operations inorder to construct or define the devices embodied on the semiconductorwafer 108.

FIG. 2 illustrates cross sections of example IC die manufactured inaccordance with one or more aspects generally at 200. In this example, afirst IC die 202 includes devices with optimized oxide gate featuresthat are thinner than oxide gates of other devices and a second IC die204 includes devices with optimized oxide gate features that are thickerthat oxide gates of other devices. In some aspects, the tools ofoperating environment 100 are used to provide various features, such asthe optimized oxide gate features, of the IC dies 202 and 204. Theimplementation and use of these gate features vary, and are describedthroughout the disclosure.

As shown in FIG. 2, the IC die 202 includes features directed totransistor gate structures for multiple respective devices, which areconfigured as a programmable memory device 206, a processor core device208, and an input/output (I/O) device 210. The programmable memorydevice 206 may be programmed through or using a metal gate 212 and anoxide gate 214, which in some cases may be broken down via programmingvoltage to form a conductive path through the programmable memory device206. The processor core device 208 also includes features directed totransistor structures, including a metal gate 216 and an oxide gate 218by which operation of the processor core device 208 is controlled.Similarly, the I/O device 210, which provides an interface orconnectivity to circuitry external to the IC die, utilizes a transistorstructure including a metal gate 220 and an oxide gate 222. Alternatelyor additionally, the IC die 202 may include non-transistor features,such as a shallow trench isolation (STI) features 224-1 through 224-4 toelectrically isolate the devices from one another or other sections ofthe IC die.

In some aspects, the oxide gates 214, 218, and 222 of the IC die 202 arefabricated with the tools described with respect to FIG. 1. For example,the masks 118, 120 may be configured to fabricate the IC die 202 suchthat the programmable memory device oxide gate 214 is physically thinnerthan the processor core device oxide gate 218. To do so, the first mask118 may be configured to expose radiated light to a portion of a layerof photoresist material that covers a gate area of the programmablememory device and also expose the radiated light a portion of the layerof photoresist material that covers a gate area of the processor coredevice. Also, as part of this configuration, the first mask 118 mayocclude the radiated light from a portion of the layer of photoresistmaterial that covers a gate area of an I/O device.

To provide the IC die 202, the second mask 120 may be configured toexpose radiated light to a portion of a layer of photoresist materialthat covers the gate area of the programmable memory device. Also, aspart of this configuration, the second mask may occlude the radiatedlight from a portion of the layer of photoresist material that coversthe gate area the processor core device and also occlude the radiatedlight from a portion of the layer of photoresist material that coversthe gate area of the I/O device. Performing two masking cycles with themasks 118, 120 configured as such may provide a programmable memorydevice oxide gate 214 that is physically thinner than a processor coredevice oxide gate 218. The thinner oxide gate 214 of the programmablememory device may enable the programmable memory device 206 to beprogrammed with a programming voltage (e.g., approximately two volts)that is lower than a programming voltage (e.g., approximately fourvolts) of conventionally implemented programmable memory devices.

As another example, consider the IC die 204 of FIG. 2 that includestransistor structures for multiple respective devices. Here, thetransistors are configured as a programmable memory device 226, aprocessor core device 228, and an input/output (I/O) device 230. Theprogrammable memory device 226 may be programmed through or usingtransistor features including a metal gate 232 and an oxide gate 234,which in some cases may be broken down via programming voltage to form aconductive path through the programmable memory device 226. Theprocessor core device 228 may be controlled using a transistor thatincludes a metal gate 236 and an oxide gate 238. Similarly, a transistorof the I/O device 240, which provides an interface or connectivity tocircuitry external to the IC die, can include a metal gate 230 and anoxide gate 242. Alternately or additionally, the IC die 204 may includenon-transistor features, such as a shallow trench isolation (STI)features 244-1 through 244-4 to electrically isolate the devices fromone another or other sections of the IC die.

In some aspects, the oxide gates 234, 238, and 242 of the IC die 204 arefabricated with the tools described with respect to FIG. 1. For example,the masks 118, 120 may be configured to fabricate the IC die 204 suchthat the programmable memory device oxide gate 234 is physically thickerthan the processor core device oxide gate 238. To do so, the first 118mask may be configured to expose radiated light to a portion of a layerof photoresist material that covers a gate area of the programmablememory device and also expose the radiated light to a portion of thelayer of photoresist material that covers a gate area of the processorcore device. Also, as part of this configuration, the first mask 118 mayocclude the radiated light from a portion of the layer of photoresistmaterial that covers a gate area of an I/O device.

To provide the IC die 204, the second mask 120 may be configured toexpose radiated light to a portion of a layer of photoresist materialthat covers the gate area of the processor core device. Also, as part ofthis configuration, the second mask 120 may occlude the radiated lightfrom a portion of the layer of photoresist material that covers the gatearea the processor core device and also occlude the radiated light froma portion of the layer of photoresist material that covers the gate areaof the I/O device. Performing two masking cycles with the masks 118, 120configured as such may provide a programmable memory device with anoxide gate 234 being physically thicker than the processor core deviceoxide gate 238. The thicker oxide gate 234 of the programmable memorydevice 226 may reduce gate leakage of the programmable memory device.

Techniques for Optimizing Gate Oxide Thickness

The following discussion describes techniques for optimizing gate oxidethicknesses. In some cases, the techniques are implemented to optimizegate oxide thickness of programmable memory devices being fabricated ona semiconductor wafer, such as semiconductor wafer 108. These techniquescan be implemented using any of the environments and entities describedherein, such as the lithography tool 102, etch tool 104, deposition tool106, and/or masks 118 and 120. These techniques include methodsillustrated in FIGS. 3 and 5, each of which is shown as a set ofoperations performed by one or more entities. These methods are notnecessarily limited to the orders of operations shown. Rather, any ofthe operations may be repeated, skipped, substituted, or re-ordered toimplement various aspects described herein. Further, these methods maybe used in conjunction with one another, in whole or in part, whetherperformed by the same entity, separate entities, or any combinationthereof. In portions of the following discussion, reference will be madeto operating environment 100 of FIG. 1 and entities of FIG. 2 by way ofexample. Such reference is not to be taken as limiting described aspectsto operating environment 100 but rather as illustrative of one of avariety of examples.

FIG. 3 illustrates an example method 300 for fabricating oxide gates ofprogrammable memory devices that are thinner than other oxide gates ofan IC die, including operations performed by the lithography tool 102,etch tool 104, and deposition tool 106 of FIG. 1.

At 302, gate areas of programmable memory devices and processor devicesof an IC die being fabricated on a semiconductor wafer are exposed andgate areas of I/O devices of the IC die are occluded. In some cases, alithography mask is positioned relative the semiconductor wafer on whichthe IC die is embodied via a mask mechanism or wafer mechanism of alithography tool. Generally, the semiconductor wafer includes a siliconsubstrate that is configured to provide respective features of theprogrammable memory devices, processor devices, and I/O devices for theIC die. The semiconductor wafer may also include a layer of oxidematerial and a layer of photoresist material over the layer of oxidematerial. Light or other energy radiated through the lithography maskmay interact with exposed portions of the photoresist material, such asover the gate areas of the programmable memory devices and processordevices of the IC die. After being exposed to light or energy, thesemiconductor wafer may then be developed to remove portions ofphotoresist material to enable etching respective portions of theunderlying oxide material. It is also possible, at 302, for exposure andocclusion of areas to be performed using more than one lithography mask.

By way of example, consider FIG. 4 in which a semiconductor wafer isillustrated at various stages of fabrication. As shown at 400, thesemiconductor wafer 108 is patterned using light 402 that is radiatedfrom the light source 112 of the lithography tool 102. The semiconductorwafer 108 includes a silicon substrate 404 that is configured viaprevious fabrication processes to have one or more IC die, each IC diehaving at least a programmable memory device gate area 406, a processorcore device gate area 408, and an I/O device gate area 410. Here, thesemiconductor wafer 108 is received with a first layer of an oxidematerial 412 and a first layer of photoresist material 414. At thelithography tool 102, the semiconductor wafer 108 is positioned relativeto the first mask 118. In this example, the first mask 118 is configuredto allow the radiated light 402 to radiate through the first mask 118and interact with portions of the first layer of photoresist material414 covering at least the programmable memory device gate area 406 andprocessor core device gate area 408. The first mask 118 is alsoconfigured to prevent, via an opaque section 416, radiated light 402from radiating through the first mask 118 to other portions of the firstlayer photoresist material 414, such as that covering the I/O devicegate area 410.

As shown at 400, the opaque section 416 occludes (e.g., covers orblocks) the I/O device gate area 410 from the light source 112 andprevents the radiated light 402 from interacting with the first layer ofphotoresist material 414 that covers the I/O device gate area 410. Afterthe semiconductor wafer 108 is patterned via the radiated light 402, thesemiconductor wafer 108 is developed by a developing tool (not shown) toremove portions of the first layer of photoresist material 414. In somecases, the first layer of photoresist material 414 is positive in natureand, as the semiconductor wafer 108 is developed, portions of the firstlayer of photoresist material 414 that interacted with the radiatedlight 402 are dissolved by a developing solution and removed. In othercases, the first layer of photoresist material 414 is negative in natureand, as the semiconductor wafer 108 is developed, portions of the firstlayer of photoresist material 414 that did not interact with theradiated light 402 are dissolved by the developing solution and removed.In such cases, the pattern of the first mask 118 may be reversed fromthat shown in FIG. 4 such that the I/O device gate area 410 is exposedto the radiated light 402.

At 304, a first layer of oxide material is etched from exposed gateareas of the programmable memory devices and the processor core devicesof the IC die. The oxide material is also etched from other portions ofthe IC die that are exposed by the removal of photoresist material.Generally, the oxide material can be etched from a semiconductor waferon which the IC die is embodied using any suitable etchant fluid, suchas a chemical liquid, plasma gas, and the like. Alternately oradditionally, the semiconductor wafer can be presented to an ashing toolafter etching, in which case photoresist remaining on the IC die may beremoved.

Continuing the ongoing example and as shown at 418, the semiconductorwafer 108 is etched by the etch tool 104 to remove the portions of thefirst layer of oxide material 412 that were covered by thepreviously-exposed portions of the first layer of photoresist material414. Here, 418 illustrates a state of the semiconductor wafer 108 thatresults from the first layer of photoresist material 414 being apositive photoresist material, the exposed portions of which weredeveloped to permit the underlying oxide material to be etched from thesurface of the wafer.

In contrast to the developed portions, a portion 420 of the first layerof photoresist material 414 that was not irradiated by the light 402protects a respective portion 422 of the first layer of oxide material412 covering the I/O device gate area 410 from being etched off thesurface of the semiconductor wafer 108. As such, the portion 422 of thefirst layer of oxide material 412 remains on the semiconductor wafer 108to form a base oxide layer over the I/O gate device area 410. Afteretching the unprotected portions of the first layer of oxide material412 from the semiconductor wafer 108, an ashing tool removes remainingportions of the first layer of photoresist material 414 that were notirradiated, such as the portion 420 of the first layer of photoresistmaterial 414 covering the I/O gate device area 410.

At 306, a second layer of oxide material covering the gate areas of theprogrammable memory devices, the processor core devices, and the I/Odevices of the IC die is formed. This second layer of oxide material maybe blanketly formed, deposited, or grown on the surface of the IC die.In the context of the present example and as shown at 424, a secondlayer of oxide material 426 is deposited by the deposition tool 106 ontothe surface of the semiconductor wafer 108. Here, note that the secondlayer of oxide material 426 is thicker on the I/O gate device area 410due to the second layer of oxide material 426 being formed at 428 on theremaining portion 422 of the first layer of oxide material 412.

At 308, gate areas of programmable memory devices of the IC die areexposed and gate areas of processor core devices and I/O devices of theIC die are occluded. In some cases, the one or more lithography masksare positioned relative to a semiconductor wafer on which the IC die isembodied via a mask mechanism or wafer mechanism of a lithography tool.The semiconductor wafer may also include a layer of oxide material and alayer of photoresist material over the oxide material. Light or otherenergy radiated through the one or more lithography masks may interactwith exposed portions of the photoresist material, such as portions overthe gate areas of the programmable memory devices of the IC die. Afterbeing exposed to light or energy, the semiconductor wafer may then bedeveloped to remove portions of photoresist material to enable etchingof respective portions of the underlying oxide material.

Continuing with the ongoing example and as shown at 430, thesemiconductor wafer 108 is patterned with the light 402 radiated fromthe light source 112 of the lithography tool 102. Here, assume that thesemiconductor wafer 108 is received with a second layer of photoresistmaterial 432 that is applied by a coating tool (not shown) betweenstates depicted at 424 and 430. At 430, the second mask 120 isconfigured to prevent radiated light 402 from radiating through opaqueareas 434 and 436. The radiated light 402 interacts with portions of thesecond layer of photoresist material 432 covering the programmablememory device gate area 406 and does not interact with portions of thesecond layer of photoresist material 432 covering the processor coredevice gate area 408 or the I/O device gate area 410.

After stage 430, the semiconductor wafer 108 is developed on adeveloping tool (not shown) to remove portions of the second layer ofphotoresist material 432. In some cases, the second layer of photoresistmaterial 432 is positive in nature and, as the semiconductor wafer 108is developed, portions of the second layer of photoresist material 432that interacted with the radiated light 402 are dissolved by adeveloping solution and removed. In other cases, the second layer ofphotoresist material 432 is negative in nature and, as the semiconductorwafer 108 is developed, portions of the second layer of photoresistmaterial 432 that did not interact with the radiated light 402 aredissolved by the developing solution and removed. In such cases, thepattern of the second mask 120 may be reversed from that shown in FIG. 4such that portions of the second layer of photoresist material 432covering the device processor gate area 404 and the I/O device gate area410 are exposed to the radiated light 402.

At 310, the second layer of oxide material is etched from the exposedgate areas of the programmable memory devices of IC die. The secondlayer of oxide material is also etched from other portions of the IC diethat are exposed by the removal of the second layer of photoresistmaterial. Generally, oxide material can be etched from the semiconductorwafer on which the IC die is embodied using any suitable etchant fluid,such as a chemical liquid, plasma gas, and the like. Alternately oradditionally, the semiconductor wafer can be presented to an ashing toolafter etching, in which instance photoresist remaining on the IC die maybe removed.

In the context of the present example and as shown at 438, thesemiconductor wafer 108 is etched by the etch tool 104. During etchingat 438, the memory device gate area 406 is exposed while the processorcore device gate area 408 and the I/O device gate area 410 are protectedfrom the etching by respective portions 440, 442 of the second layer ofphotoresist material 432. Here, 438 illustrates a state of thesemiconductor wafer that results from the second layer of photoresistmaterial 432 being a positive photoresist material, the exposed portionsof which were developed to permit the underlying oxide material to beetched from the surface of the wafer.

In contrast to the developed portions, portions 440, 442 of the secondlayer of photoresist material 432 that were not irradiated by the light402 protect respective portions 444, 446 of the layers of oxide materialcovering the processor device gate area 408 and the I/O device gate area410 from being etched off the semiconductor wafer 108. As such, theseportions 444, 446 of the oxide material remain on the semiconductorwafer 108 to form, or increase a thickness of, oxide layers over theprocessor device gate area 408 and I/O device gate area 410. Afteretching the unprotected portions of the layer of oxide material 426 fromthe semiconductor wafer 108, an ashing tool removes remaining portionsof the second layer of photoresist material 432 that were notirradiated, such as the portions 440, 442 of the second layer ofphotoresist material 432.

At 312, a third layer of oxide material covering the respective gateareas of the programmable memory devices, the processor core devices,and the I/O devices of the IC die is formed. This third layer of oxidematerial may be blanketly formed, deposited, or grown on the surface ofthe IC die. Concluding the present example and as shown at 448, a thirdlayer of oxide material 450 is deposited by the deposition tool 106 tothe semiconductor wafer 108. As a result of operations of method 300,the oxide material 450 covering the programmable memory device gate area406 is optimized for the programmable memory device with a firstthickness 452 that is thinner than a second, combined thickness 454 ofthe combined layers of oxide material 456 covering the processor coredevice gate area 408. This may be effective to provide a programmablememory device with an optimized gate oxide thickness such that aprogramming voltage of the programmable memory device that is lower thanother conventionally implemented memory devices. Thus, programmingcircuitry associated with the programmable memory device with optimizedgate oxide thickness may be implemented to generate and operate withlower on-die voltages. This in turn may reduce the complexity,isolation, and cost of the programming circuitry, thereby enabling ICdies to be implemented at lower cost, with less silicon footprint, andless power consumption. Alternately or additionally, a subsequentfabrication process may form topological asperities at oxide gateinterfaces of the programmable memory devices to further optimize theoxide gate of the programmable memory device for a lower programmingvoltage.

FIG. 5 illustrates an example method 500 for fabricating oxide gates ofprogrammable memory devices that are thicker than other oxide gates ofan IC die. The operations can be performed by the lithography tool 102,etch tool 104, and deposition tool 106 of FIG. 1.

At 502, gate areas of programmable memory devices and processor devicesof an IC die fabricated on a semiconductor wafer are exposed and gateareas are occluded. In some cases, one or more lithography masks arepositioned relative the semiconductor wafer containing the IC die via amask mechanism or wafer mechanism of a lithography tool. Generally, thesemiconductor wafer includes a silicon substrate that is configured toprovide respective features of the programmable memory devices,processor devices, and I/O devices for the IC die. The semiconductorwafer may also include a layer of oxide material and a layer ofphotoresist material over the layer of oxide material. Light or otherenergy radiated through the lithography mask may interact with exposedportions of the photoresist material, such as over the gate areas of theprogrammable memory devices and processor devices of the IC die. Afterbeing exposed to light or energy, the semiconductor wafer may then bedeveloped to remove portions of photoresist material to enable etchingrespective portions of the underlying oxide material.

By way of example, consider FIG. 6, in which a semiconductor wafer isillustrated at various stages of fabrication. As shown at 600, asemiconductor wafer 108 is patterned using light 602 that is radiatedfrom the light source 112 of the lithography tool 102. The semiconductorwafer 108 includes a silicon substrate 604 that is configured viaprevious fabrication processes to have one or more IC die, each IC diewith at least a programmable memory device gate area 606, a processorcore device gate area 608, and an I/O device gate area 610. Here, thesemiconductor wafer 108 is received with a first layer of an oxidematerial 612 and a first layer of photoresist material 614. At thelithography tool 102, the semiconductor wafer 108 is positioned relativeto the first mask 118. In this example, the first mask 118 is configuredto allow the radiated light 602 to radiate through the first mask 118and interact with portions of the first layer of photoresist material614 covering at least the programmable memory device gate area 606 andthe processor core device gate area 608. The first mask is alsoconfigured to prevent, via an opaque section 616, the radiated light 602from radiating through the first mask 118 to other portions of the firstlayer of photoresist material 614, such as that covering the I/O devicegate area 610.

As shown at 600, the opaque section 616 occludes (e.g., covers orblocks) the I/O device gate area 610 from the light source 112 andprevents the radiated light 602 from interacting with the first layer ofphotoresist material 614 that covers the I/O device gate area 610. Afterthe semiconductor wafer 108 is patterned via the radiated light 602, thesemiconductor wafer 108 is developed by a developing tool (not shown) toremove portions of the first layer of photoresist material 614. In somecases, the first layer of photoresist material 614 is positive in natureand, as the semiconductor wafer 108 is developed, portions of the firstlayer of photoresist material 614 that interacted with the radiatedlight 602 are dissolved by a developing solution and removed. In othercases, the first layer of photoresist material 614 is negative in natureand, as the semiconductor wafer is developed, portions of the firstlayer of photoresist material 614 that did not interact with theradiated light 602 are dissolved by the developing solution and removed.In such cases the pattern of the first mask may be reversed from thatshown in FIG. 6 such that the I/O device area 610 is exposed to theradiated light 602.

At 504, a first layer of oxide material is etched from exposed gateareas of the programmable memory devices and processor core devices ofthe IC die. The oxide material is also etched from other portions of theIC die that are exposed by the removal of the photoresist material. Theoxide material can be etched from a semiconductor wafer containing theIC die using any suitable etchant fluid, such as a chemical liquid,plasma gas, and the like. Alternately or additionally, the semiconductorwafer can be presented to an ashing tool after etching, in whichinstance photoresist remaining on the IC die may be removed.

Continuing the ongoing example and as shown at stage 618, thesemiconductor wafer 108 is etched by the etch tool 104 to remove theportions of the first layer of oxide material 612 that were covered bythe previously-exposed portions of the first layer of photoresistmaterial 614. Here, stage 618 illustrates a state of the semiconductorwafer 108 that results from the first layer of photoresist material 614being a positive photoresist material, the exposed portions of whichwere developed to permit the underlying oxide material to be etched fromthe surface of the wafer.

In contrast to the developed portions, a portion 620 of the first layerof photoresist material 614 that was not irradiated by the light 602protects a respective portion 622 of the first layer of oxide material612 covering the I/O device gate area 610 from being etched off thesurface of the semiconductor wafer 108. As such, the portion 622 of thefirst layer of oxide material 612 remains on the semiconductor wafer 108to form a base oxide layer over the I/O gate device area 610. Afteretching the unprotected portions of the first layer of oxide material612 from the semiconductor wafer 108, an ashing tool removes remainingportions of the first layer of photoresist material 614 that were notirradiated, such as the portion 620 of the first layer of photoresistmaterial 614 covering the I/O gate device area 610.

At 506, a second layer of oxide material covering the gate areas of theprogrammable memory devices, processor core devices, and I/O devices ofthe IC die is formed. This second layer of oxide material may beblanketly formed, deposited, or grown on the surface of the IC die. Inthe context of the present example and as shown at 624, a second layerof oxide material 626 is deposited by the deposition tool 106 onto thesurface of the semiconductor wafer 108. Here, note that the second layerof oxide material 626 is thicker on the I/O gate device area 610 due tothe second layer of oxide material 626 being formed at 628 on theremaining portion 622 of the first layer of oxide material 612.

At 508, gate areas of processor core devices of the IC die are exposedand gate areas of the I/O devices are occluded. In some cases, one ormore lithography masks are positioned relative to a semiconductor waferof the IC die via a mask mechanism or wafer mechanism of a lithographytool. The semiconductor wafer may also include a layer of oxide materialand a layer of photoresist material over the oxide material. Light orother energy radiated through the one or more lithography masks mayinteract with exposed portions of the photoresist material, such asportions over the gate areas of the processor core devices of the ICdie. After being exposed to light or energy, the semiconductor wafer maythen be developed to remove portions of photoresist material to enableetching of respective portions of the underlying oxide material.

Continuing with the ongoing example and as shown at 630, thesemiconductor wafer 108 is patterned with the light 602 radiated fromthe light source 112 of the lithography tool 102. Here, assume that thesemiconductor wafer 108 is received with a second layer of photoresistmaterial 632 that is applied by a coating tool (not shown) betweenstates depicted at 624 and 630. At 630, the second mask 120 isconfigured to prevent radiated light 602 from radiating through opaqueareas 634 and 636. The radiated light 602 interacts with portions of thesecond layer of photoresist material 632 covering the processor coredevice gate area 608 and does not interact with portions of the secondlayer of photoresist material 632 covering the programmable memorydevice gate area 606 or the I/O device gate area 610.

After stage 630, the semiconductor wafer 108 is developed on adeveloping tool (not shown) to remove portions of the second layer ofphotoresist material 632. In some cases, the second layer of photoresistmaterial 632 is positive in nature and, as the semiconductor wafer 108is developed, portions of the second layer of photoresist material 632that interacted with the radiated light 602 are dissolved by adeveloping solution and removed. In other cases, the second layer ofphotoresist material 632 is negative in nature and, as the semiconductorwafer 108 is developed, portions of the second layer of photoresistmaterial 632 that did not interact with the radiated light 602 aredissolved by the developing solution and removed. In such cases, thepattern of the second mask 120 may be reversed from that shown in FIG. 6such that portions of the second layer of photoresist material 632covering the programmable memory gate area 606 and the I/O device gatearea 610 are exposed to the radiated light 602.

At 510, the second layer of oxide material is etched from the exposedgate areas of the processor core devices of the IC die. The second layerof the oxide material is also etched from other portions of the IC diethat are exposed by the removal of the second layer of photoresistmaterial. Generally, oxide material can be etched from a semiconductorwafer containing the IC die using any suitable etchant fluid, such as achemical liquid, plasma gas, and the like. Alternately or additionally,the semiconductor wafer can be presented to an ashing tool afteretching, in which instance photoresist remaining on the IC die may beremoved.

In the context of the present example and as shown at 638, thesemiconductor wafer 108 is etched by the etch tool 104. During etchingat 638, the processor core device gate area 608 is exposed while theprogrammable memory device gate area 606 and the I/O device gate area610 are protected from the etching by respective portions 640, 642 ofthe second layer of photoresist material 632. Here, 638 illustrates astate of the semiconductor wafer that results from the second layer ofphotoresist material 632 being a positive photoresist material, theexposed portions of which were developed to permit the underlying oxidematerial to be etched from the surface of the wafer.

In contrast to the developed portions, portions 640, 642 of the secondlayer of photoresist material 632 that were not irradiated by the light602 protect respective portions 644, 646 of the layers of oxide materialcovering the programmable memory device gate area 606 and I/O devicegate area 610 from being etched off the semiconductor wafer 108. Assuch, these portions 644, 646 of the oxide material remain on thesemiconductor wafer 108 to form, or increase a thickness of, oxidelayers over the programmable memory device gate area 606 and the I/Odevice gate area 610. After etching the unprotected portions of thesecond layer of oxide material 626 from the semiconductor wafer 108, anashing tool removes remaining portions of the second layer ofphotoresist material 632 that were not irradiated, such as the portions640, 642 of the second layer of photoresist material 632.

At 512, a third layer of oxide material covering the respective gateareas of the programmable memory devices, processor core devices, andI/O devices of the IC die is formed. This third layer of oxide materialmay be blanketly formed, deposited, or grown on the surface of the ICdie. Concluding the present example and as shown at 648, a third layerof oxide material 624 is deposited by the deposition tool 106 to thesemiconductor wafer 108. As a result of operations of method 500, thecombined layers of oxide material 650 covering the programmable memorydevice gate area 606 is optimized for the programmable memory devicewith a first, combined thickness 652 that is thicker than a secondthickness 654 of the layer of oxide material 624 covering the processorcore device gate area 608. This may be effective to provide aprogrammable memory device with an optimized gate oxide thickness suchthat transistor gate leakage is reduced and reliability of theprogrammable memory device is improved. Alternately or additionally, asubsequent fabrication process may form topological asperities at oxidegate interfaces of the programmable memory devices to further optimizethe oxide gate of the programmable memory device for a lower programmingvoltage.

System-on-Chip

FIG. 7 illustrates an exemplary System-on-Chip (SoC) 700 that isimplemented with an integrated-circuit (IC) die 702 having devices thatmay be provided in accordance with various aspects described herein. TheSoC 700 can be implemented in any suitable device, such as asmart-phone, cellular phone, netbook, tablet computer, server, wirelessrouter, network-attached storage, camera, smart appliance, printer, aset-top box, or any other suitable type of device. Although describedwith reference to a SoC, the IC die 702 may also be implemented in anetwork interface controller (NIC), system-in-package (SIP),application-specific standard part (ASSP), digital signal processor(DSP), programmable SoC (PSoC), or field-programmable gate array (FPGA).

In this example, the IC die 702 includes transistors that are configuredas multiple types of devices through which respective functionalities ofthe SoC 700 can be implemented. The device types of the IC die 702include input-output (I/O) devices 704, processor core devices 706, andprogrammable memory device 708. The I/O devices 704 may be implementedas I/O circuitry, such as digital or analog interfaces to entitiesexternal to the SoC 700. The processor devices 706 of the IC die 702 maybe configured as a microprocessor of the SoC 700 (e.g., any of amicrocontroller, processor core, application processor, or DSP) forexecuting processor-executable instructions from storage media (notshown) on which the instructions and other information are embodied.

The programmable memory devices 708 of the IC die 700 may be configuredas any suitable type of programmable or non-volatile memory, such asone-time programmable (OTP) memory or multiple-time programmable (MTP)memory. In some cases, the programmable memory is configured aselectronic anti-fuse memory in which bits of memory cells are set bybreaking down an oxide gate of a memory cell transistor effective toprovide a low impedance path or “short” through the memory cell. By sodoing, a value of the memory cell can be set to a “1” or “0” dependingon a bit value convention of the programmable memory devices. To programthe programmable memory devices 708, the IC die 702 includes a memorydevice programming circuit 710 to store bits or values to theprogrammable memory devices 708.

In some aspects, the memory device programming circuit 710 is configuredto apply, based on bit address information, a programming voltage to anoxide gate of a corresponding programmable memory device 708 such thatthe oxide gate of the transistor is physically altered. This may includealtering the oxide gate effective to provide a low impedance path or“short” through the transistor. By so doing, the bit value at theaddress is programmed for subsequent reading via sense circuitry (notshown) and the bit value of the programmable memory device 708 isretained in a persistent state without a need for power to refresh ormaintain the memory cell (e.g., non-volatile).

As described herein, the oxide gate of the programmable memory device708 can be fabricated at a thickness optimized for a specificprogramming voltage in relation to operating voltages of other deviceson the IC die 702. For example, the transistor of the programmablememory device 708 can be fabricated with an optimized gate oxidethickness that is thinner than that of other devices of the IC 702. Byso doing, a programming voltage of the programmable memory device withoptimized gate oxide thickness may be reduced compared to a programmingvoltage of a conventionally implemented programmable memory device. Insome cases, the programming voltage of the programmable memory device isapproximately twice a voltage at which the core processor devices 702operate. In contrast, a programming voltage of a conventionalprogrammable memory device may be four to five times an operatingvoltage of a processor device having a same gate oxide thickness. Assuch, the memory device programming circuit 710 can be implemented togenerate and operate with lower on-die voltages, which allows theprogramming circuit to be implemented with less isolation, reducedcomplexity, and in a smaller design space than those associated withconventional (e.g., higher voltage) programmable memories.

The devices of the IC die 702, either independently or in combinationwith other entities of the SoC 700, can be implemented with any suitablecombination of semiconductor features or circuitry to implement variousaspects and/or features of entities or devices described herein. The ICdie 702 may also be provided integral with other entities of the SoC700, such as integrated with an I/O logic interface, a memorycontroller, or non-volatile memory of the SoC 700. Alternately oradditionally, the IC die 702 and the devices thereof can be implementedas hardware, firmware, fixed logic circuitry, or any combinationthereof.

Further aspects of the present disclosure relate to one or more of thefollowing clauses.

A method includes exposing respective gate areas of programmable memorydevices and processor core devices of an integrated-circuit (IC) die andoccluding gate areas of input/output (I/O) devices of the IC die. Afirst layer of material is etched from the exposed respective gate areasof the programmable memory devices and the processor core devices. Asecond layer of oxide material is formed on the IC die, coating therespective gate areas of the programmable memory devices, the processorcore devices, and the I/O devices. The gate areas of the programmablememory devices are exposed and the respective gate areas of theprocessor core devices and the I/O devices are occluded. The secondlayer of oxide material is etched from the exposed gate areas of theprogrammable memory device. A third layer of oxide material is formed onthe IC die, coating the respective gate areas of the programmable memorydevices, the processor core devices, and the I/O devices of the IC die.

In the method, a thickness of the third layer of oxide material on thegate areas of the programmable memory devices is less than a combinedthickness of the second and third layers of oxide material on the gateareas of the processor core devices.

In the method, exposing the respective gate areas of the processor coredevices and programmable memory devices of the IC die and occluding gateareas of I/O devices of the IC die comprises depositing a photoresistmaterial, radiating light through the one or more lithography masks, anddeveloping the photoresist material.

In the method, the photoresist material is a positive photoresistmaterial.

In the method, forming of the first layer of oxide material, the secondlayer of oxide material, or the third layer of oxide material forms alayer of silicon oxynitride material, a layer of silicon dioxidematerial, or a layer of silicon nitride material.

In the method, the first, the second, or the third layer of oxidematerial is formed via chemical vapor deposition across the IC die.

The method may further comprise forming topographical asperities in thethird layer of oxide material at oxide-gate interfaces of theprogrammable memory devices.

Another method includes exposing respective gate areas of programmablememory devices and processor core devices of an integrated-circuit (IC)die and occluding gate areas of input/output (I/O) devices of the ICdie. A first layer of oxide material is etched from the exposedrespective gate areas of the programmable memory devices and theprocessor core devices. A second layer of oxide material is formed onthe IC die, coating the respective gate areas of the programmable memorydevices, the processor core devices, and the I/O devices. Gate areas ofthe processor core devices are exposed and respective gate areas of theprogrammable memory devices and the I/O devices are occluded. The secondlayer of material is etched from the exposed gate areas of the processorcore devices. A third layer of oxide material is formed on the IC die,the third layer of oxide material coating the respective gate areas ofthe programmable memory devices, the processor core devices, and the I/Odevices of the IC die.

In the method, a thickness of the third layer of oxide material on thegate areas of the programmable memory devices is greater than a combinedthickness of the second and third layers of oxide material on the gateareas of the processor core devices.

In the method, exposing the gate areas of the processor core devices andoccluding the respective gate areas of the programmable memory devicesand the I/O devices comprises deposition of a photoresist material,radiation of light through one or more lithography masks, and developingthe photoresist material.

In the method, the photoresist material is a positive photoresistmaterial.

In the method, forming of the first layer of oxide material, the secondlayer of oxide material, or the third layer of oxide material forms alayer of silicon oxynitride material, a layer of silicon dioxidematerial, or a layer of silicon nitride material.

In the method, the first layer of oxide material, the second layer ofoxide material, or the third layer of oxide material is formed viachemical vapor deposition across the IC die.

The method may also include forming topographical asperities in thethird layer of oxide material at oxide-gate interfaces of theprogrammable memory devices.

An integrated-circuit (IC) die comprises input/output (I/O) deviceshaving oxide gates of a first thickness and core processor deviceshaving oxide gates of a second thickness, the second thickness of theoxide gates of the core processor devices being different from the firstthickness of the oxide gates of the I/O devices. Also included arenon-volatile programmable memory devices having oxide gates of a thirdthickness, the third thickness of the oxide gates of the non-volatileprogrammable memory devices being different from the second thickness ofoxide gates of the core processor devices and the first thickness ofoxide gates of the I/O devices. The IC die also includes memory deviceprogramming circuit configured to program the non-volatile memorydevices by altering respective oxide gates of the non-volatile memorydevices using a programming voltage that is approximately twice avoltage at which the processor core devices operate.

In the IC die, the third thickness of oxide gates of the non-volatileprogrammable memory devices is thinner than the second thickness of theoxide gates of the processor devices or is thicker than the secondthickness of the oxide gates of the core processor devices.

In the IC die, the non-volatile programmable memory devices areconfigured as one-time programmable (OTP) or multiple-time programmable(MTP) memory devices.

In the IC die, the memory device programming circuit configured toprogram the non-volatile memory devices programs the non-volatile memorydevices based on bit address information.

In the IC die, the oxide gates of the I/O devices, the oxide gates ofthe core processor devices, and the oxide gates of the non-volatileprogrammable memory devices are formed using a layer of siliconoxynitride material, a layer of silicon dioxide material, or a layer ofsilicon nitride material.

Although the subject matter has been described in language specific tostructural features and/or methodological operations, it is to beunderstood that the subject matter defined in the appended claims is notnecessarily limited to the specific features or operations describedherein, including orders in which they are performed.

What is claimed is:
 1. An integrated-circuit (IC) die comprising:input/output (I/O) devices having oxide gates of a first thickness; coreprocessor devices having oxide gates of a second thickness, the secondthickness of the oxide gates of the core processor devices beingdifferent from the first thickness of the oxide gates of the I/Odevices; and non-volatile programmable memory devices having oxide gatesof a third thickness, the third thickness of the oxide gates of thenon-volatile programmable memory devices being: (i) thinner than thesecond thickness of oxide gates of the core processor devices of the ICdie; and (ii) different from the first thickness of oxide gates of theI/O devices of the IC die.
 2. The IC die of claim 1, wherein thenon-volatile programmable memory devices are one-time programmable (OTP)memory devices.
 3. The IC die of claim 2, wherein the one-time (OTP)programmable memory devices are configured as electronic anti-fusememory devices.
 4. The IC die of claim 1, wherein the non-volatileprogrammable memory devices are multiple-time programmable (MTP) memorydevices.
 5. The IC die of claim 1, further comprising a memory deviceprogramming circuit configured to program the non-volatile programmablememory devices by altering respective oxide gates of the non-volatileprogrammable memory devices using a programming voltage.
 6. The IC dieof claim 5, wherein the programming voltage used by the memory deviceprogramming circuit is approximately twice a voltage at which theprocessor core devices operate.
 7. The IC die of claim 5, wherein thememory device programming circuit configured to program the non-volatileprogrammable memory devices programs the non-volatile memory devicesbased on bit address information or bit value information.
 8. The IC dieof claim 1, wherein the oxide gates of the I/O devices, the oxide gatesof the core processor devices, or the oxide gates of the non-volatileprogrammable memory devices are formed with a silicon oxynitridematerial.
 9. The IC die of claim 1, wherein the oxide gates of the I/Odevices, the oxide gates of the core processor devices, or the oxidegates of the non-volatile programmable memory devices are formed with asilicon dioxide material.
 10. The IC die of claim 1, wherein the oxidegates of the I/O devices, the oxide gates of the core processor devices,or the oxide gates of the non-volatile programmable memory devices areformed with a silicon nitride material.
 11. The IC die of claim 1,wherein the oxide gates of the non-volatile programmable memory devicesinclude topographical asperities.
 12. A System-on-Chip comprising: coreprocessor devices having oxide gates of a first thickness; non-volatileprogrammable memory devices having oxide gates of a second thickness,the second thickness of the oxide gates of the non-volatile programmablememory devices being thinner than the first thickness of oxide gates ofthe core processor devices; and a memory device programming circuitconfigured to program the non-volatile memory devices by alteringrespective oxide gates of the non-volatile memory devices using aprogramming voltage.
 13. The System-on-Chip of claim 12, wherein thenon-volatile programmable memory devices of the System-on-Chip areone-time programmable (OTP) memory devices.
 14. The System-on-Chip ofclaim 13, wherein the OTP programmable memory devices of theSystem-on-Chip are configured as electronic anti-fuse memory devices.15. The System-on-Chip of claim 12, wherein the non-volatileprogrammable memory devices of the System-on-Chip are multiple-timeprogrammable (MTP) memory devices.
 16. The System-on-Chip of claim 12,further comprising input/output (I/O) devices having oxide gates of athird thickness that is different from the second thickness of the oxidegates of the non-volatile programmable memory devices.
 17. TheSystem-on-Chip of claim 12, wherein the oxide gates of the non-volatileprogrammable memory devices are formed with one of a silicon oxynitridematerial, a silicon dioxide material, or a silicon nitride material. 18.A method performed by an integrated-circuit (IC) die, the methodcomprising: operating, by a processor of the IC die, processor coredevices of the IC die at a first voltage, the processor core deviceshaving oxide gates of a first thickness; and programming, by a memorydevice programming circuit of the IC die, non-volatile programmablememory devices of the IC die at a second voltage, wherein: thenon-volatile programmable memory devices have oxide gates of a secondthickness that is thinner than the first thickness of the oxide gates ofthe processor core devices, and the second voltage for programming thenon-volatile programmable memory devices is approximately twice thefirst voltage at which the processor core devices operate.
 19. Themethod of claim 18, wherein programming the non-volatile programmablememory devices comprises setting respective bit values of thenon-volatile programmable memory devices.
 20. The method of claim 18,further comprising operating input/output (I/O) devices of the IC die,the I/O devices having oxide gates of a third thickness that isdifferent from the second thickness of the oxide gates of thenon-volatile programmable memory devices.